Semiconductor memory devices are being developed for high integration, high performance and low cost. A word line of a semiconductor memory device formed of polysilicon has a large specific resistance that results in a large RC (resistance and capacitance) delay. The RC delay may cause an undesirable signal delay affecting the performance of the semiconductor device. To reduce the signal delay, a semiconductor memory device may be divided into a plurality of memory cell arrays. The memory cell arrays are coupled to a section row decoder and section word lines. The section row decoder generates a section row decoding signal by decoding, through logic operations, a section word line selection signal and a logic signal inputted from a main word line, wherein section word lines are selected by an output signal of the section row decoder.
The memory cell arrays are coupled to the section row decoder through the section word lines. The section word lines are tapped by a word line of each memory cell. The section word lines are tapped by the word lines to maintain signal strength; the word lines of the memory cell arrays are formed of polysilicon or tungsten having a large resistance. By implementing section word lines formed of a metal wire line having a low resistance the RC delay can be reduced as compared to a device implementing only polysilicon or tungsten word lines.
In a semiconductor memory device implementing memory cell arrays and having a two-layer metal structure, first metal wire lines form a bit line, and second metal wire lines form a section word line. A word line of a memory cell is disposed substantially orthogonal to the bit lines. The section word line is disposed in a word line direction of the memory cell, over the first metal wire lines. For large memory cells, a power line or a signal line may be formed of the second metal wire lines.
However, a wiring structure of a semiconductor memory device having the two-layer metal structure is unsuitable to a high integration application.
To obtain high-integration and high performance in a semiconductor memory device, a metal structure formed of three or more layers can be used. In a metal structure formed of three of more layer, a wiring layout structure within a cell array region becomes important. In employing a metal structure of three or more layers, parasitic capacitance increases between upper and lower metal layers, tapping for a reduction of resistance becomes more difficult, and a signal delay increases. These problems become limit factors in manufacturing semiconductor memory devices of high performance and high integration.
Therefore, a need exists for an improved layout structure in a semiconductor memory device having three or more metal layers.